S26 GIRS Seminars: Semiconductor Defect Limited and Parametric-Shift Limited Yield Modelling, a Data-based approach

📅 When: Thursday, May 28, 2026
🕐 Time: 1:00–2:00 PM PT
📍 Where: (In-Person) Engineering 6 Building, Room 580B and 💻 ZOOM

Karthik Sankaran, PhD Student

headshot of Karthik Sankaran

Abstract: The Semiconductor industry is a multi-billion dollar industry and Semiconductor Yield is a fundamental factor driving device cost. Development cost, time-to-market & yield are the most important factors of interest to the industry. Two components are associated with Semiconductor Yield: 1. Defect Limited Yield 2. Parametric-Shift limited Yield. Defect Yield is caused by random defects in the fabrication plant whereas Parametric Yield is influenced by process variations for a given design and process node. While Foundries do not share process-related data, they provide Wafer Acceptance Test data (WAT data or E-test data) which are obtained from test coupons located at specific points on the wafer. WAT data records fundamental electrical parameters such as Oxide Thickness, Threshold Voltage, Saturation Current etc. and these recordings provide a window for observing process fluctuations. This seminar will cover a methodology to improve Defect Limited Yield estimations by introducing a Process Adjustment Factor using Process node parameters and a methodology to model Parametric Shift using Machine Learning methodologies on WAT data and Wafer sort data.

Short Bio: Karthik Sankaran is a Ph.D. Student in Materials Science and Engineering at the University of California, Los Angeles and is a Graduate Researcher in the B. John Garrick Institute for Risk Sciences (GIRS). He obtained his B. Tech. in Metallurgical Engineering and Materials Science at the Indian Institute of Technology in 2018. Some of his previous works include Simulation of Hydrogel formation, First-Principle analysis of Metal-Oxides, Risk analysis and Modelling of Traffic Collision Avoidance Systems (TCAS) and Development of Risk-based Decision making tool for Covid-19. Currently his research interests include Semiconductor Yield Estimation and Statistics-based Yield Modelling of Application-Specific Integrated Circuits (ASICs).