W26 GIRS Seminars: New Challenges in ASIC Reliability in the Age of AI
/When: Thursday, March 12, 2026
Time: 1:00pm PT
Where: (In-Person) UCLA Engineering 6 BLDG, Rm 580B and ZOOM
Kamran Hakim
headshot of Kamran Hakim
Abstract: The rise of AI has introduced critical, unprecedented challenges for HPC component reliability. This is driven by the need for extreme performance, massive data bandwidth, and 24/7 operation. Advanced process nodes (e.g., 5nm, 3nm) are used to achieve higher performance at lower power. However, the shift towards HPC design has created a triad of challenges:
Performance (obtained at lower nodes)
Power dissipation (often exceeding 700W per unit)
Reliability (becomes more challenging)
Squeezing maximum performance often jeopardizes long-term stability. A new approach is required to meet reliability goals.
Kamran Hakim / ASIC Reliability Engineer at Teradyne
Educational background: MS in Material Science & Engineering / Surface Chemistry & Solid-State Physics
Experience / Places I worked: I have been working in the semiconductor industry for 44 years. 16 years in manufacturing (process engineering). 28 years in device & systems reliability. 1- Intel Corp; 2- Digital Equipment Corp; 3- Western Digital Corp.; 4- Teradyne Corp.
Professional philosophy: Work is worship! By this I mean work is not simply daily labor to make money to satisfy my needs. Work is rather an expression of reverence for, joy in participating in and admiration for engineering & the scientific process upon which it stands.
What I like outside of work: Studying philosophy, teaching, classical music, cooking, travelling, etc…
